From Turing Machines to Central Processing Units
How do we get from a Turing Machine to the CPU in your computer? A Turing Machine has a tape for storing information, a CPU has memory. A Turing Machine has a set of rules, a CPU has an instruction set. A Turing Machine looks on the tape for a symbol and applies a rule, possibly changing the value. The CPU looks into memory and performs an operation, potentially changing values. With the Universal Turing Machine [UTM] descriptions of other Turing Machines were encoded on to the tape and the read by the UTM. After the UTM has read the description, it simulates the encoded Turing Machine. On a computer, programs are stored in memory and executed by the CPU.
So at a very high level that is how a computer works. Reading the instructions of a program tells the CPU what to do.
So how does it actually work? Every CPU understands a set of rules, or instructions. All the instructions that a CPU understands is called its instruction set. A program is composed of instructions and data. The CPU has a pointer, the instruction pointer, which points into the instructions of the executing program. The CPU takes the instruction pointed to by the instruction pointer, executes it and then moves the instruction pointer to the next instruction.
After executing most instructions the instruction pointer moves to the next instruction in memory. However certain instructions change the value of the instruction pointer to somewhere else. Such instructions are often referred to as jump instructions. There are unconditional jumps, jumps that, when executed, always change the value of the instruction pointer. However most jumps are conditional jumps. Conditional jumps will change the instruction pointer only if a condition is met, otherwise the instruction pointer is moved to the next instruction in memory. Conditional jumps allow programs to control the flow of execution.
Other instructions perform mathematical operations (add, multiply, etc), memory operations (copying data from one location to another, etc), comparisons (equality, greater than, etc) and there are many others.
How quickly a CPU can execute instructions determines how "fast" a CPU is. So what determines how quickly a computer can execute instructions? It is basically determined by the clock. Most CPUs are designed so that everything is synchronized. To maintain this synchronisity the clock sends a signal to every component in the CPU. When the components receive this signal they perform an operation. The faster the clock the more operations the CPU can execute. This is where the term clock speed comes from. Clock speed is measured in Hertz (Hz) the number of signal cycles per second. 100 Hz is 100 signals in a second. Modern processors are currently measured in Gigahertz. 1 Gigahertz is 1 billion (1 000 000 000) cycles per second.
Now the question is, what limits the clock speed of a CPU? The short answer is technology. The longer answer follows. CPUs consume electricity and produce information and heat. Information is the intended output, heat is waste. Like most waste if it collects it causes damage. If a CPU gets too hot it stops working properly and can potentially get damaged. There are two ways to deal with heat, one is to get rid of the heat, the other is to make the CPU produce less heat. The first is not so interesting, unless you are a mad overclocker. Instead lets consider controlling the heat output.
Heat is created when electricity moves through wires. The more resistance to the movement of electricity, the more heat is generated. So heat can be reduced by reducing the resistance to the flow of electricity. One way to do this is by making the wires smaller. Smaller wires means less resistance and so less heat. One may have read or heard about CPU's being manufactured with a 0.13 micron process (or some other similar number). A micron is a measure of width (1 micrometer, or one millionth of a meter). Thus a smaller process means narrower connections and less heat production.
The less connections in a CPU, the less wires there are for electricity to flow through and so the less heat is produced. So a simpler CPU, one with less connections generates less heat and can run faster. This leads to a interesting design decision. CISC (Complex instruction set computers) verses RISC (Reduced instruction set computers). A CISC computer sacrifices simplicity of CPU for more powerful instructions. A RISC computer has a simpler CPU and because of this is able to run at a higher clock speed. For example a CISC computer may be able to compute sin(x) in as a single instruction, whereas the RISC computer computes this value in software, thus requiring multiple instructions. Therefore at the same clock speed the CISC computer will be faster. However the RISC computer should able to achieve greater clock speeds, and so the RISC computer might be faster in general leading to a faster computer.
An interesting example of this is the Intel Pentium 4 and AMD Athlon. When first released the P4 seemed unimpressive. At the same clock speed as competitors (and previous Intel processors) it benchmarks slower. As time went on Intel was able to increase the clock speed of the P4 beyond that of its competitors. The AMD Athlon is faster that the P4 at the same clock speed. However at the time of writing, the Athlon's top clock speed is 2.2 GHz, which benchmarks about the same speed and the P4 at 3.0 Ghz (AMD claims speed equivalence of 3.2 GHz, but the benchmarkers don't agree).
Update: As time progressed AMD was able to increase the clock speed of the Athlon to achieve better performance then the P4. The P4 was, in fact, hampered by the amount of heat it generated. As of 2006 Intel is shifting to lower clock speeds and better "performance per watt" which really means, how much speed they can get relative to the amount of power the chip draws. This is important for laptops and rack mounted servers.
A new innovation may put the RISC vs CISC debate to bed. Mirco-operations [micro-ops] allow a RISC core to execute CISC instructions. The CPU is able to decode a single CISC style instructions into multiple micro-ops which then execute on a RISC style core. In reality this is really just a RISC computer that simulates CISC instructions in hardware. However it seems to be a good compromise between the two.